1. Field of the Invention
This invention relates to a method of fabrication used for semiconductor integrated circuit devices and more specifically to a method of activation prior to electroless copper plating for achieving highly selective complete interconnect metal line and via/contact hole fill.
2. Description of Related Art
As semiconductor integrated circuits are constantly being scaled down to the deep submicron regime, multiple layers of interconnections are thus required so as to meet the increase in the packing density. Vias/contact holes between successive layers of interconnections have had to have almost near vertical sidewalls with high aspect ratios and have had to be placed at smaller spacing intervals to fulfill such requirement. Subsequent metallization processes are thus necessary to fill the vias/contact holes completely without voids with high conductivity metal such as copper.
Various techniques of deposition of copper have been known which, in general, include electroplating, electroless plating, sputtered chemical and physical vapor deposition. Among these, the electroless method appears preferable based on considerations like the cost of the fabrication process, the ease of execution of the process and the complete filling capability of the process. However, in general, prior to such electroless plating, an adhesive/catalytic seeding layer like Pd or CVD (Chemical Vapor Deposition) Cu has had to be laid down to facilitate subsequent plating and high selectivity of the plating is very much desired such that a majority of the plated Cu is deposited in the interconnect metal lines and the vias/contact holes.
In U.S. Pat. No. 5,167,992 (issued to Charles W. C. Lin et al on Dec. 1, 1992), a selective electroless plating for metal conductors disposed on a dielectric surface is disclosed. The method includes removing a carbonized film from the dielectric surface by a plasma discharge, acid treating the metal conductor in a first acid solution, activating the metal conductor, and deactivating the dielectric surface in a second acid solution, followed by electroless plating to overcoat a metal on the metal conductor only.
Also, in U.S. Pat. No. 5,017,516 (granted to Andreas M. T. P. van der Putten), a method of performing electroless plating selectively in contact holes through selective nucleations using a low concentration of PdCl2 is disclosed.
U.S. Pat. No. 5,443,865 entitled xe2x80x9cMethod for Conditioning a Substrate for Subsequent Electroless Metal Depositionxe2x80x9d (issued to Tisdale, et al on Aug. 22, 1995), discloses a method whereby electrochemically generated reducing agents are adsorbed by a substrate which is then in contact with a seeding medium to deposit Palladium seed for subsequent electroless and electrolytic metallization.
U.S. Pat. No. 4,869,930 entitled xe2x80x9cMethod for Preparing Substrates for Deposition of Metal Seed from An Organometallic Vapor for Subsequent Blectroless Metallizationxe2x80x9d (granted to Clarke, et al on Sep. 26, 1989) describes a process whereby a volatile organometallic compound is allowed to react with active chemical sites initially adsorbed on a substrate to form a species of the metal constituent of the compound which may then be transformed into a free metal to serve as a seed for subsequent electroless deposition. When selective deposition is desired, a resist masking layer is used prior to forming the seed layer.
U.S. Pat. No. 5,674,787 entitled xe2x80x9cSelective Electroless Copper Deposited Interconnect Plugs for USLI Applicationsxe2x80x9d discloses a method utilising electroless copper deposition to selectively form encapsulated copper plugs in vias of a semiconductor, to connect conductive regions on the semiconductor.
With the above prior art techniques, growth of plugs has been achieved by activation of a surface of a barrier material in a base of the vias followed by electroless deposition of metal on the activated surface. In the case of U.S. Pat. No. 5,674,787 the barrier material is a diffusion barrier material such as titanium nitride (TiN) and the deposited metal is copper. In order to activate the TiN the semiconductor is treated in an activation solution which includes a surfactant to facilitate seeding of Cu on the TiN. Use of a surfactant such as polyethylene glycol or Triton X-100 can, however, introduce hydrocarbons into the vias which may effect reliable operation of the plug.
It is an object of the invention to provide a new method of forming plugs in a via/contact hole in a semiconductor without requiring selective activation of a barrier surface in a base of the hole.
In accordance with the invention there is provided a method of fabrication for a semiconductor integrated circuit device, including:
providing a semiconductor substrate having an insulating layer with a contact hole formed therein and a diffusion barrier provided on sidewalls and a base of the hole;
forming a film of polysilicon on a surface of the substrate in which the hole is provided;
subjecting the said substrate to an activation aqueous solution;
forming an activation layer comprising copper seedings on the said polysilicon;
rinsing said semiconductor substrate to remove said aqueous solution;
depositing copper on the activation layer by electroless copper deposition such the copper forms into said hole to fill the contact hole and thereby provide a plug without voids;
rinsing said semiconductor substrate; and
applying chemical-mechanical polishing to remove said polysilicon and excess copper external of said hole to thereby provide the substrate with a smooth topography.